staging: rtl8192e: Rework EEPROM handling code

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Card configuration is stored in SPI EEPROM (93c46 or 93c56)
working in 128|256x16 mode.
Communication is handled using GPIO bitbang.

>From behaviour perspective, delay after read was removed.
It is not needed as we wait after reading GPIO mapped to
PCI-E register - it should have no side effects.

According to sample EEPROM datasheet (AT93Cx6), max frequency for
worst case scenario (1.8V supply) is 250kHZ (vs. 1MHz for 5V).
Driver generates ~50kHZ clock - margin should be big enough
even for devices from other vendors.

Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

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This commit is contained in:

Mateusz Kulikowski 2015-07-30 23:48:50 +02:00 • committed by Greg Kroah-Hartman

parent fdc792cd1b

commit 08582d83e5

2 changed files with 43 additions and 85 deletions

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8

drivers/staging/rtl8192e/rtl8192e/r8192E_hw.h

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124

drivers/staging/rtl8192e/rtl8192e/rtl_eeprom.c

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