clk: tegra20: Add DEV1/DEV2 OSC dividers

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CDEV1/CDEV2 clocks could have corresponding oscillator clock divider as
a parent. Add these dividers in order to be able to provide that parent
option.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Marcel Ziswiler <marcel@ziswiler.com>
Tested-by: Marcel Ziswiler <marcel@ziswiler.com>
Tested-by: Marc Dietrich <marvin24@gmx.de>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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Dmitry Osipenko 2018-05-08 19:26:03 +03:00 • committed by Thierry Reding

parent 60cc43fc88

commit 08a52593fc

1 changed files with 14 additions and 0 deletions

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drivers/clk/tegra/clk-tegra20.c

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