drm/amdgpu: Skip program SDMA0_SEM_WAIT_FAIL_TIMER_CNTL under SRIOV VF

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[Why]
As SDMA0_SEM_WAIT_FAIL_TIMER_CNTL is a PF-only register,
L1 would block this register for VF access.

[How]
VF do not program it.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Yifan Zha <Yifan.Zha@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

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Yifan Zha 2022-08-17 18:44:14 +08:00 • committed by Alex Deucher

parent 40ad3e545b

commit 08c8442c4a

1 changed files with 2 additions and 1 deletions

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drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

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