MIPS: HTW: Prevent accidental HTW start due to nested htw_{start, stop}

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commit ed4cbc81ad upstream.

activate_mm() and switch_mm() call get_new_mmu_context() which in turn
can enable the HTW before the entryhi is changed with the new ASID.
Since the latter will enable the HTW in local_flush_tlb_all(),
then there is a small timing window where the HTW is running with the
new ASID but with an old pgd since the TLBMISS_HANDLER_SETUP_PGD
hasn't assigned a new one yet. In order to prevent that, we introduce a
simple htw counter to avoid starting HTW accidentally due to nested
htw_{start,stop}() sequences. Moreover, since various IPI calls can
enforce TLB flushing operations on a different core, such an operation
may interrupt another htw_{stop,start} in progress leading inconsistent
updates of the htw_seq variable. In order to avoid that, we disable the
interrupts whenever we update that variable.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9118/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

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Markos Chandras 2015-01-26 13:04:33 +00:00 • committed by Greg Kroah-Hartman

parent b3b345af59

commit 09f2e748e0

4 changed files with 32 additions and 8 deletions

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5

arch/mips/include/asm/cpu-info.h

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7

arch/mips/include/asm/mmu_context.h

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24

arch/mips/include/asm/pgtable.h

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4

arch/mips/kernel/cpu-probe.c

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