x86/sev: Mark the TSC in a secure TSC guest as reliable

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In SNP guest environment with Secure TSC enabled, unlike other clock sources
(such as HPET, ACPI timer, APIC, etc), the RDTSC instruction is handled
without causing a VM exit, resulting in minimal overhead and jitters. Even
when the host CPU's TSC is tampered with, the Secure TSC enabled guest keeps
on ticking forward. Hence, mark Secure TSC as the only reliable clock source,
bypassing unstable calibration.

  [ bp: Massage. ]

Signed-off-by: Nikunj A Dadhania <nikunj@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Tom Lendacky <thomas.lendacky@amd.com>
Tested-by: Peter Gonda <pgonda@google.com>
Link: https://lore.kernel.org/r/20250106124633.1418972-10-nikunj@amd.com

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Nikunj A Dadhania 2025-01-06 18:16:29 +05:30 • committed by Borislav Petkov (AMD)

parent eef679a4b5

commit 0a2a98f691

1 changed files with 3 additions and 0 deletions

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arch/x86/mm/mem_encrypt_amd.c

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