riscv: errata: Fix the PAUSE Opcode for MIPS P8700

Add ERRATA_MIPS and ERRATA_MIPS_P8700_PAUSE_OPCODE configs. Handle errata for the MIPS PAUSE instruction. Signed-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com> Signed-off-by: Aleksandar Rikalo <arikalo@gmail.com> Signed-off-by: Raj Vishwanathan4 <rvishwanathan@mips.com> Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com> Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com> Link: https://lore.kernel.org/r/20250724-p8700-pause-v5-7-a6cbbe1c3412@htecgroup.com [pjw@kernel.org: updated to apply and compile; fixed a checkpatch issue] Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-11-08 18:57:22 +00:00 · 2025-07-24 17:23:31 +02:00 · 2025-07-24 17:23:31 +02:00 · 0b0ca959d2
commit 0b0ca959d2
parent c9a9fc2322
12 changed files with 127 additions and 3 deletions
--- a/arch/riscv/Kconfig.errata
+++ b/arch/riscv/Kconfig.errata
--- a/arch/riscv/errata/Makefile
+++ b/arch/riscv/errata/Makefile
--- a/arch/riscv/errata/mips/Makefile
+++ b/arch/riscv/errata/mips/Makefile
--- a/arch/riscv/errata/mips/errata.c
+++ b/arch/riscv/errata/mips/errata.c
--- a/arch/riscv/include/asm/alternative.h
+++ b/arch/riscv/include/asm/alternative.h
--- a/arch/riscv/include/asm/cmpxchg.h
+++ b/arch/riscv/include/asm/cmpxchg.h
--- a/arch/riscv/include/asm/errata_list.h
+++ b/arch/riscv/include/asm/errata_list.h
--- a/arch/riscv/include/asm/errata_list_vendors.h
+++ b/arch/riscv/include/asm/errata_list_vendors.h
--- a/arch/riscv/include/asm/vdso/processor.h
+++ b/arch/riscv/include/asm/vdso/processor.h
--- a/arch/riscv/kernel/alternative.c
+++ b/arch/riscv/kernel/alternative.c
--- a/arch/riscv/kernel/entry.S
+++ b/arch/riscv/kernel/entry.S
--- a/arch/riscv/mm/init.c
+++ b/arch/riscv/mm/init.c