drm/amdgpu: add indirect r/w interface for smn address greater than 32bits

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On multiple AIDs platform, bit[34:32] in SMD address is leveraged to access
nonAID0 register smn address and new PCI_INDEX_HI register is introduced
to access the higher bits.

v2: rebase on latest register accessors (Alex)

Signed-off-by: Le Ma <le.ma@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

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Le Ma 2022-04-02 19:39:59 +08:00 • committed by Alex Deucher

parent 1526ec9a3e

commit 0c552ed387

5 changed files with 118 additions and 0 deletions

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11

drivers/gpu/drm/amd/amdgpu/amdgpu.h

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98

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

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1

drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h

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6

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

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2

drivers/gpu/drm/amd/amdgpu/soc15.c

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