drm/i915/icl: Add Wa_1406609255

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Shader feature to prefetch binding tables does not support 16:6 18:8 BTP
formats. Enabling fault handling could result in hangs with faults.
Disabling demand prefetch would disable binding table prefetch.

V2: Fix the stepping rivision to B0(Mika)

References: HSDES#1406609255, HSDES#1406573985
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181004182939.7668-5-radhakrishna.sripada@intel.com

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Radhakrishna Sripada 2018-10-04 11:29:38 -07:00 • committed by Mika Kuoppala

parent f53a70bd93

commit 0c7d2aedf5

2 changed files with 9 additions and 0 deletions

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3

drivers/gpu/drm/i915/i915_reg.h

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6

drivers/gpu/drm/i915/intel_workarounds.c

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