drm/i915/cx0: program DDI_CLK_VALFREQ with DDI clock frequency

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DDI_CLK_VALFREQ is programmed with the port clock, which for DP is the
symbol clock computed assuming 8b/10b encoding (link_rate / 10). For
DP 128b/132b (UHBR) rates and for HDMI FRL the port clock needs to
be modfied.
DDI_CLK_VALFREQ does not have any functional impact on H/w, it
only records the frequency S/w intends to set.
Use intel_ddi_link_symbol_clock() to write the correct DDI clock in
kHz.

Fixes: 51390cc0e0 ("drm/i915/mtl: Add Support for C10 PHY message bus and pll programming")
Fixes: 73fc3abcb7 ("drm/i915/mtl: Enabling/disabling sequence Thunderbolt pll")
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patch.msgid.link/20260811175844.2613721-3-suraj.kandpal@intel.com
(cherry picked from commit 9ac3ee6c0f)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

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Suraj Kandpal 2026-08-11 23:28:43 +05:30 • committed by Jani Nikula

parent 900f48940a

commit 0cd42b346d

1 changed files with 3 additions and 2 deletions

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drivers/gpu/drm/i915/display/intel_cx0_phy.c

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