phy: cadence: Sierra: Add PCIe + SGMII PHY multilink configuration

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Add register sequences for PCIe + SGMII PHY multilink configuration.
This has been validated on TI J7 platforms.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230403085644.10187-1-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

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Swapnil Jakhade 2023-04-03 10:56:44 +02:00 • committed by Vinod Koul

parent 45810d486b

commit 0cfa43ab46

1 changed files with 139 additions and 2 deletions

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drivers/phy/cadence/phy-cadence-sierra.c

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