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drm/nouveau/ltc/gp10b: Add custom L2 cache implementation

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There are extra registers that need to be programmed to make the level 2
cache work on GP10B, such as the stream ID register that is used when an
SMMU is used to translate memory addresses.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Thierry Reding 2019-12-09 13:00:04 +01:00 • committed by Ben Skeggs
commit 0d0d498265
5 changed files with 70 additions and 1 deletions
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