perf/x86: Hybrid PMU support for hardware cache event

Browse source

The hardware cache events are different among hybrid PMUs. Each hybrid
PMU should have its own hw cache event table.

Suggested-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/1618237865-33448-9-git-send-email-kan.liang@linux.intel.com

...

This commit is contained in:

Kan Liang 2021-04-12 07:30:48 -07:00 • committed by Peter Zijlstra

parent eaacf07d11

commit 0d18f2dfea

2 changed files with 11 additions and 3 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

5

arch/x86/events/core.c

View file

9

arch/x86/events/perf_event.h

View file