clk: meson-gxbb: Add GXL/GXM GP0 Variant

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The clock tree in the Amlogic GXBB and GXL/GXM SoCs is shared, but the GXL/GXM
SoCs embeds a different GP0 PLL, and needs different parameters with a vendor
provided reduced rate table.

This patch adds the GXL GP0 variant, and adds a GXL DT compatible in order
to use the GXL GP0 PLL instead of the GXBB specific one.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/1490178747-14837-4-git-send-email-narmstrong@baylibre.com

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Neil Armstrong 2017-03-22 11:32:25 +01:00 • committed by Kevin Hilman

parent e194401cf4

commit 0d48fc558d

2 changed files with 275 additions and 28 deletions

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301

drivers/clk/meson/gxbb.c

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2

drivers/clk/meson/gxbb.h

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