ASoC: intel: board: sof_rt5682: Update rt1015 pll input clk freq

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In commit d696a61413 ("ASoC: rt1015: Add condition to prevent SoC
providing bclk in ratio of 50 times of sample rate."), PLL input at 50fs
is no longer supported, the new recommended settings at 48Khz rate are:

PLL input       SSP bclk
------------------------
64fs            3.073Mhz
100fs           4.8Mhz

(bclk update is reflected in topoplogy.)

Signed-off-by: Yong Zhi <yong.zhi@intel.com>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Link: https://lore.kernel.org/r/20200717211337.31956-6-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>

...

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Yong Zhi 2020-07-17 16:13:36 -05:00 • committed by Mark Brown

parent 6b540ac763

commit 0d95d06a7a

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1 changed files with 8 additions and 1 deletions

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sound/soc/intel/boards/sof_rt5682.c

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