drm/i915/dg1: Enable DPLL for DG1

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Add DG1 DPLL Enable register macro and use the macro to enable the
correct DPLL based on PLL id. Although we use
_MG_PLL1_ENABLE/_MG_PLL2_ENABLE these are rather combo phys.

While at it, fix coding style: wrong newlines and use if/else chain

v2: Rewrite original patch from Aditya Swarup based on refactors
upstream

Bspec: 49443, 49206

Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Aditya Swarup <aditya.swarup@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201014191937.1266226-6-lucas.demarchi@intel.com

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This commit is contained in:

Lucas De Marchi 2020-10-14 12:19:32 -07:00

parent b71b477d94

commit 0dac17af0a

2 changed files with 8 additions and 4 deletions

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8

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

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4

drivers/gpu/drm/i915/i915_reg.h

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