clk: renesas: r9a09g077: Propagate rate changes to parent clocks

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[ Upstream commit 145dfd70b9 ]

Add the CLK_SET_RATE_PARENT flag to divider clock registration so that rate
changes can propagate to parent clocks when needed. This allows the CPG
divider clocks to request rate adjustments from their parent, ensuring
correct frequency scaling and improved flexibility in clock rate selection.

Fixes: 065fe720ee ("clk: renesas: Add support for R9A09G077 SoC")
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251028165127.991351-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Sasha Levin <sashal@kernel.org>

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Lad Prabhakar 2025-10-28 16:51:23 +00:00 • committed by Greg Kroah-Hartman

parent 4dd34a24b6

commit 0dcbf7d6e9

1 changed files with 2 additions and 2 deletions

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drivers/clk/renesas/r9a09g077-cpg.c

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