arm64: mm: Add support for folding PUDs at runtime

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In order to support LPA2 on 16k pages in a way that permits non-LPA2
systems to run the same kernel image, we have to be able to fall back to
at most 48 bits of virtual addressing.

Falling back to 48 bits would result in a level 0 with only 2 entries,
which is suboptimal in terms of TLB utilization. So instead, let's fall
back to 47 bits in that case. This means we need to be able to fold PUDs
dynamically, similar to how we fold P4Ds for 48 bit virtual addressing
on LPA2 with 4k pages.

Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Link: https://lore.kernel.org/r/20240214122845.2033971-81-ardb+git@google.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

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Ard Biesheuvel 2024-02-14 13:29:22 +01:00 • committed by Catalin Marinas

parent 0383808e4d

commit 0dd4f60a2c

6 changed files with 95 additions and 13 deletions

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12

arch/arm64/include/asm/pgalloc.h

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89

arch/arm64/include/asm/pgtable.h

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arch/arm64/include/asm/tlb.h

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arch/arm64/kernel/cpufeature.c

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arch/arm64/mm/mmu.c

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arch/arm64/mm/pgd.c

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