clk: renesas: r9a09g047: Add CLK_PLLDSI{0,1}_DIV7 clocks

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Add the CLK_PLLDSI0_DIV7 and CLK_PLLDSI1_DIV7 fixed-factor clocks to
the r9a09g047 SoC clock driver.

These clocks are required to enable LVDS0 and LVDS1 output support.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Link: https://patch.msgid.link/e50c1721e1dc160e8b4518e8c5172f10cba4b58b.1775636898.git.tommaso.merciai.xr@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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Tommaso Merciai 2026-04-08 12:36:49 +02:00 • committed by Geert Uytterhoeven

parent 6913a61596

commit 0e1597c688

1 changed files with 5 additions and 0 deletions

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drivers/clk/renesas/r9a09g047-cpg.c

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