soc: sunxi: Add Allwinner D1 PPU driver

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The PPU contains a series of identical MMIO register ranges, one for
each power domain. Each range contains control/status bits for a clock
gate, reset line, output gates, and a power switch. (The clock and reset
are separate from, and in addition to, the bits in the CCU.) It also
contains a hardware power sequence engine to control the other bits.

Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Link: https://lore.kernel.org/r/20230126063419.15971-3-samuel@sholland.org
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>

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Samuel Holland 2023-01-26 00:34:18 -06:00 • committed by Jernej Skrabec

parent 84def5abbb

commit 0e30ca5ab0

3 changed files with 216 additions and 0 deletions

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8

drivers/soc/sunxi/Kconfig

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1

drivers/soc/sunxi/Makefile

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207

drivers/soc/sunxi/sun20i-ppu.c

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