ice: Fix quad registers read on E825

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[ Upstream commit dc26548d72 ]

Quad registers are read/written incorrectly. E825 devices always use
quad 0 address and differentiate between the PHYs by changing SBQ
destination device (phy_0 or phy_0_peer).

Add helpers for reading/writing PTP registers shared per quad and use
correct quad address and SBQ destination device based on port.

Fixes: 7cab44f1c3 ("ice: Introduce ETH56G PHY model for E825C products")
Reviewed-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com>
Tested-by: Pucha Himasekhar Reddy <himasekharx.reddy.pucha@intel.com> (A Contingent worker at Intel)
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

...

This commit is contained in:

Karol Kolacinski 2024-11-05 13:29:14 +01:00 • committed by Greg Kroah-Hartman

parent 605c7381b5

commit 0e5a802fcf

2 changed files with 133 additions and 87 deletions

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219

drivers/net/ethernet/intel/ice/ice_ptp_hw.c

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1

drivers/net/ethernet/intel/ice/ice_type.h

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