dmaengine: qcom_hidma: protect common data structures

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When MSI interrupts are supported, error and the transfer interrupt can
come from multiple processor contexts.

Each error interrupt is an MSI interrupt. If the channel is disabled by
the first error interrupt, the remaining error interrupts will gracefully
return in the interrupt handler.

If an error is observed while servicing the completions in success case,
the posting of the completions will be aborted as soon as channel disabled
state is observed. The error interrupt handler will take it from there and
finish the remaining completions. We don't want to create multiple success
and error messages to be delivered to the client in mixed order.

Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>

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Sinan Kaya 2016-10-21 12:37:58 -04:00 • committed by Vinod Koul

parent 9483d9ae09

commit 0e858f8d6f

1 changed files with 11 additions and 33 deletions

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44

drivers/dma/qcom/hidma_ll.c

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