drm/i915/skl: Flush the WM configuration

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When we write new values for the DDB allocation and WM parameters, we now
need to trigger the double buffer update for the pipe to take the new
configuration into account.

As the DDB is a global resource shared between planes, enabling or
disabling one plane will result in changes for all planes that are
currently in use, thus the need write PLANE_SURF/CUR_BASE for more than
the plane we're touching.

v2: Don't wait for pipes that are off

v3: Split the staging results structure to not exceed the 1Kb stack
    allocation in skl_update_wm()

v4: Rework and document the algorithm after Ville found that it was all
    wrong.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

...

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Damien Lespiau 2014-11-04 17:07:02 +00:00 • committed by Daniel Vetter

parent 34bb56af7f

commit 0e8fb7ba7c

1 changed files with 135 additions and 0 deletions

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drivers/gpu/drm/i915/intel_pm.c

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