m68knommu: support version 2 ColdFire split cache

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The newer version 2 ColdFire CPU cores support a configurable cache
arrangement. The cache memory can be used as all instruction cache, all
data cache, or split in half for both instruction and data caching.
Support this setup via a Kconfig time menu that allows a kernel builder
to choose the arrangement they want to use.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>

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Greg Ungerer 2010-11-09 15:31:08 +10:00

parent d475e3e473

commit 0ef6c9b8f7

2 changed files with 48 additions and 14 deletions

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30

arch/m68k/include/asm/m52xxacr.h

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32

arch/m68knommu/Kconfig

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