drm/amdgpu: Flush TLB after mapping for VG20+XGMI

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For VG20 + XGMI bridge, all mappings PTEs cache in TC, this may have
stall invalid PTEs in TC because one cache line has 8 pages. Need always
flush_tlb after updating mapping.

Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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Philip Yang 2022-04-01 15:30:12 -04:00 • committed by Alex Deucher

parent 34452ac303

commit 0f12a22f37

1 changed files with 6 additions and 0 deletions

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drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

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