clk: tegra: Allow PLLE training to succeed

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Under some circumstances the PLLE needs to be retrained, in which case
access to the PMC registers is required. Fix this by passing a pointer
to the PMC registers instead of NULL when registering the PLLE clock.

Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

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Thierry Reding 2013-03-14 16:27:05 +01:00 • committed by Mike Turquette

parent 07961ac7c0

commit 0f1bc12e9e

1 changed files with 1 additions and 1 deletions

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drivers/clk/tegra/clk-tegra20.c

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