clk: renesas: r9a09g057: Add clock and reset entries for ISP

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Add entries detailing the clocks and resets for the ISP in the
RZ/V2H(P) SoC.

Signed-off-by: Daniel Scally <dan.scally@ideasonboard.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251010-rzv2h_isp_clk-v2-1-2c8853a9af7c@ideasonboard.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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Daniel Scally 2025-10-10 10:43:10 +01:00 • committed by Geert Uytterhoeven

parent e43b186df5

commit 0f537c4183

2 changed files with 16 additions and 0 deletions

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14

drivers/clk/renesas/r9a09g057-cpg.c

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2

drivers/clk/renesas/rzv2h-cpg.h

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