clk: at91: Fix division by zero in PLL recalc_rate()

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Commit a982e45dc1 ("clk: at91: PLL recalc_rate() now using cached MUL
and DIV values") removed a check that prevents a division by zero. This
now causes a stacktrace when booting the kernel on a at91 platform if
the PLL DIV register contains zero. This commit reintroduces this check.

Fixes: a982e45dc1 ("clk: at91: PLL recalc_rate() now using cached...")
Cc: <stable@vger.kernel.org>
Signed-off-by: Ronald Wahl <rwahl@gmx.de>
Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

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Ronald Wahl 2018-10-10 15:54:54 +02:00 • committed by Stephen Boyd

parent 5b394b2ddf

commit 0f5cb0e622

1 changed files with 3 additions and 0 deletions

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drivers/clk/at91/clk-pll.c

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