mlxsw: reg: Add counter fields to RITR register

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Update RITR for counter support. This allows adding counters for
ASIC's router ports.

Signed-off-by: Arkadi Sharshevsky <arkadis@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

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Arkadi Sharshevsky 2017-03-28 17:24:11 +02:00 • committed by David S. Miller

parent 1555d204e7

commit 0f630fcbe5

1 changed files with 54 additions and 0 deletions

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drivers/net/ethernet/mellanox/mlxsw/reg.h

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