PCI/ASPM: Add L1 substate capability structure register definitions

Add L1 substate capability structure register definitions for use in
subsequent patches.  See the PCIe r3.1 spec, sec 7.33.

[bhelgaas: add PCIe spec reference]
Signed-off-by: Rajat Jain <rajatja@google.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
This commit is contained in:
Rajat Jain 2017-01-02 22:34:10 -08:00 • committed by Bjorn Helgaas
commit 0fc1223f0e