ARM: dts: socfpga: update NAND clocking for c5/a5

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The NAND IP needs 3 clocks(nand_x_clk, nand_clk, and nand_ecc_clk). The
nand_x_clk and nand_ecc_clk are derived from the nand_clk. The nand_x_clk
has a fixed divider of 4.

Also, update the NAND dts property with the correct clocks property.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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v2: add nand_ecc_clk and update commit message

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Dinh Nguyen 2018-07-09 17:16:00 -05:00

parent 12b2982a1f

commit 0ffc5df823

1 changed files with 10 additions and 2 deletions

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arch/arm/boot/dts/socfpga.dtsi

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