From 725351152a7d0c9cdd7072724d1e4d3e7c452f9a Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Tue, 7 Apr 2026 16:36:23 +0100 Subject: [PATCH 01/10] riscv: dts: microchip: add tsu clock to macb on pic64gx In increment mode, the tsu clock for the macb is provided separately to the pck, usually the same clock as the reference to the rtc provided by an off-chip oscillator. pclk is 150 MHz typically, and the reference is either 100 MHz or 125 MHz, so having the tsu clock is required for correct rate selection. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/pic64gx.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/pic64gx.dtsi b/arch/riscv/boot/dts/microchip/pic64gx.dtsi index c164d7bc270a..e9ec376b1776 100644 --- a/arch/riscv/boot/dts/microchip/pic64gx.dtsi +++ b/arch/riscv/boot/dts/microchip/pic64gx.dtsi @@ -459,8 +459,8 @@ interrupts = <64>, <65>, <66>, <67>, <68>, <69>; /* Filled in by a bootloader */ local-mac-address = [00 00 00 00 00 00]; - clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>; - clock-names = "pclk", "hclk"; + clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>, <&refclk>; + clock-names = "pclk", "hclk", "tsu_clk"; resets = <&mss_top_sysreg CLK_MAC0>; status = "disabled"; }; @@ -475,8 +475,8 @@ interrupts = <70>, <71>, <72>, <73>, <74>, <75>; /* Filled in by a bootloader */ local-mac-address = [00 00 00 00 00 00]; - clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>; - clock-names = "pclk", "hclk"; + clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>, <&refclk>; + clock-names = "pclk", "hclk", "tsu_clk"; resets = <&mss_top_sysreg CLK_MAC1>; status = "disabled"; }; From 4ce4a46cdb2404bcd53ca58a18aeda673f37fbe9 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Tue, 7 Apr 2026 16:36:24 +0100 Subject: [PATCH 02/10] riscv: dts: microchip: update pic64gx gpio interrupts to better match the SoC Just like PolarFire SoC, the same issues with GPIO interrupts exist in the pic64gx, due to their similarity. Yoinking from the commit message for the same change for PolarFire SoC: There are 3 GPIO controllers on this SoC, of which: - GPIO controller 0 has 14 GPIOs - GPIO controller 1 has 24 GPIOs - GPIO controller 2 has 32 GPIOs All GPIOs are capable of generating interrupts, for a total of 70. There are only 41 IRQs available however, so a configurable mux is used to ensure all GPIOs can be used for interrupt generation. 38 of the 41 interrupts are in what the documentation calls "direct mode", as they provide an exclusive connection from a GPIO to the PLIC. The 3 remaining interrupts are used to mux the interrupts which do not have a exclusive connection, one for each GPIO controller. The mux was overlooked when the bindings and driver were originally written for the GPIO controllers on Polarfire SoC, and the interrupts property in the GPIO nodes used to try and convey what the mapping was. Instead, the mux should be a device in its own right, and the GPIO controllers should be connected to it, rather than to the PLIC. Now that a binding exists for that mux, fix the inaccurate description of the interrupt controller hierarchy. Signed-off-by: Conor Dooley --- .../dts/microchip/pic64gx-curiosity-kit.dts | 47 ++++++++++++------- arch/riscv/boot/dts/microchip/pic64gx.dtsi | 32 +++++++++++-- 2 files changed, 58 insertions(+), 21 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts b/arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts index 2f2ccd77af30..ed3ff03f3b11 100644 --- a/arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts +++ b/arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts @@ -63,10 +63,6 @@ }; &gpio0 { - interrupts = <13>, <14>, <15>, <16>, - <17>, <18>, <19>, <20>, - <21>, <22>, <23>, <24>, - <25>, <26>; status ="okay"; gpio-line-names = "", "", "", "", "", "", "", "", @@ -74,12 +70,6 @@ }; &gpio1 { - interrupts = <27>, <28>, <29>, <30>, - <31>, <32>, <33>, <34>, - <35>, <36>, <37>, <38>, - <39>, <40>, <41>, <42>, - <43>, <44>, <45>, <46>, - <47>, <48>, <49>, <50>; status ="okay"; gpio-line-names = "", "", "LED1", "LED2", "LED3", "LED4", "LED5", "LED6", @@ -88,14 +78,6 @@ }; &gpio2 { - interrupts = <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>; pinctrl-names = "default"; pinctrl-0 = <&mdio1_gpio>, <&spi0_gpio>, <&can0_gpio>, <&pcie_gpio>, <&qspi_gpio>, <&uart3_gpio>, <&uart4_gpio>, <&can1_gpio>; @@ -107,6 +89,35 @@ "DIP4", "USR_IO11", "", "", "SWITCH1", "", "", ""; }; +&irqmux { + interrupt-map = <0 &plic 13>, <1 &plic 14>, <2 &plic 15>, + <3 &plic 16>, <4 &plic 17>, <5 &plic 18>, + <6 &plic 19>, <7 &plic 20>, <8 &plic 21>, + <9 &plic 22>, <10 &plic 23>, <11 &plic 24>, + <12 &plic 25>, <13 &plic 26>, + + <32 &plic 27>, <33 &plic 28>, <34 &plic 29>, + <35 &plic 30>, <36 &plic 31>, <37 &plic 32>, + <38 &plic 33>, <39 &plic 34>, <40 &plic 35>, + <41 &plic 36>, <42 &plic 37>, <43 &plic 38>, + <44 &plic 39>, <45 &plic 40>, <46 &plic 41>, + <47 &plic 42>, <48 &plic 43>, <49 &plic 44>, + <50 &plic 45>, <51 &plic 46>, <52 &plic 47>, + <53 &plic 48>, <54 &plic 49>, <55 &plic 50>, + + <64 &plic 53>, <65 &plic 53>, <66 &plic 53>, + <67 &plic 53>, <68 &plic 53>, <69 &plic 53>, + <70 &plic 53>, <71 &plic 53>, <72 &plic 53>, + <73 &plic 53>, <74 &plic 53>, <75 &plic 53>, + <76 &plic 53>, <77 &plic 53>, <78 &plic 53>, + <79 &plic 53>, <80 &plic 53>, <81 &plic 53>, + <82 &plic 53>, <83 &plic 53>, <84 &plic 53>, + <85 &plic 53>, <86 &plic 53>, <87 &plic 53>, + <88 &plic 53>, <89 &plic 53>, <90 &plic 53>, + <91 &plic 53>, <92 &plic 53>, <93 &plic 53>, + <94 &plic 53>, <95 &plic 53>; +}; + &mac0 { status = "okay"; phy-mode = "sgmii"; diff --git a/arch/riscv/boot/dts/microchip/pic64gx.dtsi b/arch/riscv/boot/dts/microchip/pic64gx.dtsi index e9ec376b1776..5cf3e3de0e06 100644 --- a/arch/riscv/boot/dts/microchip/pic64gx.dtsi +++ b/arch/riscv/boot/dts/microchip/pic64gx.dtsi @@ -295,6 +295,14 @@ #size-cells = <1>; #reset-cells = <1>; + irqmux: interrupt-controller@54 { + compatible = "microchip,pic64gx-irqmux", "microchip,mpfs-irqmux"; + reg = <0x54 0x4>; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0x7f>; + }; + iomux0: pinctrl@200 { compatible = "microchip,pic64gx-pinctrl-iomux0", "microchip,mpfs-pinctrl-iomux0"; @@ -484,9 +492,13 @@ gpio0: gpio@20120000 { compatible = "microchip,pic64gx-gpio", "microchip,mpfs-gpio"; reg = <0x0 0x20120000 0x0 0x1000>; - interrupt-parent = <&plic>; + interrupt-parent = <&irqmux>; interrupt-controller; #interrupt-cells = <1>; + interrupts = <0>, <1>, <2>, <3>, + <4>, <5>, <6>, <7>, + <8>, <9>, <10>, <11>, + <12>, <13>; clocks = <&clkcfg CLK_GPIO0>; gpio-controller; #gpio-cells = <2>; @@ -497,9 +509,15 @@ gpio1: gpio@20121000 { compatible = "microchip,pic64gx-gpio", "microchip,mpfs-gpio"; reg = <0x0 0x20121000 0x0 0x1000>; - interrupt-parent = <&plic>; + interrupt-parent = <&irqmux>; interrupt-controller; #interrupt-cells = <1>; + interrupts = <32>, <33>, <34>, <35>, + <36>, <37>, <38>, <39>, + <40>, <41>, <42>, <43>, + <44>, <45>, <46>, <47>, + <48>, <49>, <50>, <51>, + <52>, <53>, <54>, <55>; clocks = <&clkcfg CLK_GPIO1>; gpio-controller; #gpio-cells = <2>; @@ -510,9 +528,17 @@ gpio2: gpio@20122000 { compatible = "microchip,pic64gx-gpio", "microchip,mpfs-gpio"; reg = <0x0 0x20122000 0x0 0x1000>; - interrupt-parent = <&plic>; + interrupt-parent = <&irqmux>; interrupt-controller; #interrupt-cells = <1>; + interrupts = <64>, <65>, <66>, <67>, + <68>, <69>, <70>, <71>, + <72>, <73>, <74>, <75>, + <76>, <77>, <78>, <79>, + <80>, <81>, <82>, <83>, + <84>, <85>, <86>, <87>, + <88>, <89>, <90>, <91>, + <92>, <93>, <94>, <95>; clocks = <&clkcfg CLK_GPIO2>; gpio-controller; #gpio-cells = <2>; From 58bd7ff1a1bd9f2847aa23ff94b6ab3a39717136 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Tue, 7 Apr 2026 16:36:25 +0100 Subject: [PATCH 03/10] riscv: dts: microchip: sort pic64gx i2c nodes alphanumerically The i2c nodes are out of place, sort them where they should be. Signed-off-by: Conor Dooley --- .../boot/dts/microchip/pic64gx-curiosity-kit.dts | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts b/arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts index ed3ff03f3b11..ef5bff3093fc 100644 --- a/arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts +++ b/arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts @@ -89,6 +89,14 @@ "DIP4", "USR_IO11", "", "", "SWITCH1", "", "", ""; }; +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + &irqmux { interrupt-map = <0 &plic 13>, <1 &plic 14>, <2 &plic 15>, <3 &plic 16>, <4 &plic 17>, <5 &plic 18>, @@ -134,14 +142,6 @@ status = "okay"; }; -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - &mmc { bus-width = <4>; disable-wp; From 79b731da340f1c9703e28665d49a865aa6956278 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Thu, 19 Mar 2026 16:26:35 +0000 Subject: [PATCH 04/10] riscv: dts: microchip: gpio controllers on mpfs need 2 interrupt cells The platform has variable interrupt types for GPIO interrupts, in addition to having multiple lines per GPIO controller. Two interrupt cells are required. Fixes: 528a5b1f2556d ("riscv: dts: microchip: add new peripherals to icicle kit device tree") Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi index d535d4c72763..85d8df6437f2 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -499,7 +499,7 @@ reg = <0x0 0x20120000 0x0 0x1000>; interrupt-parent = <&irqmux>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, <9>, <10>, <11>, @@ -516,7 +516,7 @@ reg = <0x0 0x20121000 0x0 0x1000>; interrupt-parent = <&irqmux>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; interrupts = <32>, <33>, <34>, <35>, <36>, <37>, <38>, <39>, <40>, <41>, <42>, <43>, @@ -535,7 +535,7 @@ reg = <0x0 0x20122000 0x0 0x1000>; interrupt-parent = <&irqmux>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; interrupts = <64>, <65>, <66>, <67>, <68>, <69>, <70>, <71>, <72>, <73>, <74>, <75>, From 7ab032833b2f0dd3b51d71e6756ebe7efc61eed4 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Thu, 5 Mar 2026 10:30:03 +0000 Subject: [PATCH 05/10] riscv: dts: microchip: remove gpio hogs from beaglev-fire sd-det-hog should be cd-gpios, but when the mmc-spi-slot was added, the "cd-" prefix was omitted and the collision with the hog was not noticed. vio-enable-hog is just a regulator that can be modelled as such. Fixes: 1088d49b62648 ("riscv: dts: microchip: enable qspi adc/mmc-spi-slot on BeagleV Fire") Signed-off-by: Conor Dooley --- .../boot/dts/microchip/mpfs-beaglev-fire.dts | 25 ++++++++----------- 1 file changed, 10 insertions(+), 15 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts b/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts index 0e1b0b8d394b..6e9653827cfe 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts @@ -77,6 +77,15 @@ regulator-max-microvolt = <1200000>; }; + regulator-1v8-syzygy { + compatible = "regulator-fixed"; + gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; + regulator-name = "syzygy_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + enable-active-high; + }; }; &gpio0 { @@ -118,20 +127,6 @@ "P8_PIN27", "P8_PIN28", "P8_PIN29", "P8_PIN30", "M2_W_DISABLE1", "M2_W_DISABLE2", "VIO_ENABLE", "SD_DET"; status = "okay"; - - vio-enable-hog { - gpio-hog; - gpios = <30 30>; - output-high; - line-name = "VIO_ENABLE"; - }; - - sd-det-hog { - gpio-hog; - gpios = <31 31>; - input; - line-name = "SD_DET"; - }; }; &i2c0 { @@ -316,7 +311,7 @@ mmc@1 { compatible = "mmc-spi-slot"; reg = <1>; - gpios = <&gpio2 31 1>; + cd-gpios = <&gpio2 31 GPIO_ACTIVE_LOW>; voltage-ranges = <3300 3300>; spi-max-frequency = <5000000>; disable-wp; From 044427ff277021b9f750a9addf60d13db98a2f24 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Thu, 5 Mar 2026 10:12:12 +0000 Subject: [PATCH 06/10] riscv: dts: microchip: clean up beaglev-fire regulator node names Recently the binding for regulator-fixed introduced preferred naming, in the regulator-XvY format. Change the existing regulators to match this pattern. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts b/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts index 6e9653827cfe..3adcd4b193c2 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts @@ -63,14 +63,14 @@ regulator-max-microvolt = <2800000>; }; - imx219_vdig: fixedregulator-1 { + imx219_vdig: regulator-1v8 { compatible = "regulator-fixed"; regulator-name = "imx219_vdig"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - imx219_vddl: fixedregulator-2 { + imx219_vddl: regulator-1v2 { compatible = "regulator-fixed"; regulator-name = "imx219_vddl"; regulator-min-microvolt = <1200000>; From 11cec5d0f596d52f0d3d81851649281318f4b52a Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Thu, 5 Mar 2026 10:27:14 +0000 Subject: [PATCH 07/10] riscv: dts: microchip: add adc interrupt on beaglev-fire The mcp3464r on the beaglev-fire has its interrupt wired up, but not present in the devicetree. Add it. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts b/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts index 3adcd4b193c2..c79dc49c1ce0 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts @@ -4,6 +4,7 @@ /dts-v1/; #include +#include #include "mpfs.dtsi" #include "mpfs-beaglev-fire-fabric.dtsi" @@ -255,6 +256,7 @@ spi-cpha; spi-max-frequency = <5000000>; microchip,hw-device-address = <1>; + interrupts-extended = <&gpio1 20 IRQ_TYPE_LEVEL_LOW>; #address-cells = <1>; #size-cells = <0>; status = "okay"; From bba7498491dfab3ee68ab4ce6c615e5d70cfccba Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Thu, 5 Mar 2026 10:31:05 +0000 Subject: [PATCH 08/10] riscv: dts: microchip: add gpio line names on beaglev-fire GPIO controller 2 has the gpio-line-names property, but the two other controllers do not. Add the property for these controllers too. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts b/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts index c79dc49c1ce0..7bbd400b7103 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts @@ -95,6 +95,8 @@ <21>, <22>, <23>, <24>, <25>, <26>; ngpios = <14>; + gpio-line-names = "", "", "", "", "", "", "", + "", "", "", "", "", "SD_CARD_CS", "USER_BUTTON"; status = "okay"; }; @@ -106,6 +108,9 @@ <43>, <44>, <45>, <46>, <47>, <48>, <49>, <50>; ngpios = <24>; + gpio-line-names = "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", + "ADC_IRQn", "", "", "USB_OCn"; status = "okay"; }; From 48c7771b3c792b153872a2eff67e4cbcb77e4054 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Tue, 5 May 2026 11:22:50 +0100 Subject: [PATCH 09/10] riscv: dts: microchip: fix pic64gx gpio interrupt-cells As the pic64gx devicetree files got added in parallel to the GPIO interrupt-cells being fixed for PolarFire SoC, they didn't get changed to the correct values. Fix them now. Fixes: 7219d20f9f421 ("riscv: dts: microchip: add pic64gx and its curiosity kit") Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/pic64gx.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/pic64gx.dtsi b/arch/riscv/boot/dts/microchip/pic64gx.dtsi index 5cf3e3de0e06..5addfd435711 100644 --- a/arch/riscv/boot/dts/microchip/pic64gx.dtsi +++ b/arch/riscv/boot/dts/microchip/pic64gx.dtsi @@ -494,7 +494,7 @@ reg = <0x0 0x20120000 0x0 0x1000>; interrupt-parent = <&irqmux>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, <9>, <10>, <11>, @@ -511,7 +511,7 @@ reg = <0x0 0x20121000 0x0 0x1000>; interrupt-parent = <&irqmux>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; interrupts = <32>, <33>, <34>, <35>, <36>, <37>, <38>, <39>, <40>, <41>, <42>, <43>, @@ -530,7 +530,7 @@ reg = <0x0 0x20122000 0x0 0x1000>; interrupt-parent = <&irqmux>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; interrupts = <64>, <65>, <66>, <67>, <68>, <69>, <70>, <71>, <72>, <73>, <74>, <75>, From 3869417f8996fb076998342d0db560fdd795a3a6 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Fri, 15 May 2026 17:16:31 +0100 Subject: [PATCH 10/10] riscv: dts: microchip: remove redudant enabling of syscontroller The system controller is never disabled, there's no need to ever enable it. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts | 1 - arch/riscv/boot/dts/microchip/mpfs-disco-kit.dts | 4 ---- arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi | 4 ---- arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts | 4 ---- arch/riscv/boot/dts/microchip/mpfs-polarberry.dts | 4 ---- arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts | 4 ---- arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts | 4 ---- arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts | 4 ---- 8 files changed, 29 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts b/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts index 7bbd400b7103..6d7037c9528d 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts @@ -328,7 +328,6 @@ &syscontroller { microchip,bitstream-flash = <&sys_ctrl_flash>; - status = "okay"; }; &syscontroller_qspi { diff --git a/arch/riscv/boot/dts/microchip/mpfs-disco-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-disco-kit.dts index f769c9d5d7b4..da2fcde263e3 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-disco-kit.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-disco-kit.dts @@ -199,7 +199,3 @@ &spi1 { status = "okay"; }; - -&syscontroller { - status = "okay"; -}; diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi index 7816408343a3..a11e3103b8f2 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi @@ -238,10 +238,6 @@ status = "okay"; }; -&syscontroller { - status = "okay"; -}; - &syscontroller_qspi { /* * The flash *is* there, but Icicle kits that have engineering sample diff --git a/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts b/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts index 86234968df48..973e34b74be4 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts @@ -179,10 +179,6 @@ status = "okay"; }; -&syscontroller { - status = "okay"; -}; - &usb { status = "okay"; dr_mode = "host"; diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts index 510d59153cd0..cad0871a62a5 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts @@ -112,7 +112,3 @@ &rtc { status = "okay"; }; - -&syscontroller { - status = "okay"; -}; diff --git a/arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts index 8f1908a10567..46ded8a4fc36 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts @@ -149,10 +149,6 @@ status = "okay"; }; -&syscontroller { - status = "okay"; -}; - &usb { status = "okay"; dr_mode = "otg"; diff --git a/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts b/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts index bc15530a2979..c6950410e918 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts @@ -171,10 +171,6 @@ }; }; -&syscontroller { - status = "okay"; -}; - &usb { status = "okay"; dr_mode = "host"; diff --git a/arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts b/arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts index ef5bff3093fc..180fd8891903 100644 --- a/arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts +++ b/arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts @@ -170,7 +170,3 @@ &rtc { status = "okay"; }; - -&syscontroller { - status = "okay"; -};