iommu/vt-d: Follow PT_FEAT_DMA_INCOHERENT into the PASID entry

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Currently a incoherent walk domain cannot be attached to a coherent
capable iommu. Kevin says HW probably doesn't exist with such a mixture,
but making the driver support it makes logical sense anyhow.

When building the PASID entry the PWSNP (Page Walk Snoop) bit tells the HW
if it should issue snoops. If the page table is cache flushed because of
PT_FEAT_DMA_INCOHERENT then it is fine to set this bit to 0 even if the HW
supports 1.

Weaken the compatible check to permit a coherent instance to accept an
incoherent table and fix the PASID table construction to set PWSNP from
PT_FEAT_DMA_INCOHERENT.

SVA always sets PWSNP.

Reviewed-by: Lu Baolu <baolu.lu@linux.intel.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>

...

This commit is contained in:

Jason Gunthorpe 2025-10-23 15:22:37 -03:00 • committed by Joerg Roedel

parent d373449d8e

commit 101a285411

4 changed files with 22 additions and 19 deletions

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8

drivers/iommu/intel/iommu.c

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31

drivers/iommu/intel/pasid.c

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1

drivers/iommu/intel/pasid.h

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1

drivers/iommu/intel/svm.c

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