pinctrl: tegra: Renumber the GG.0 and GG.1 pins

Browse source

There is no need to define these at a specific offset since they are the
only pins defined for this SoC generation. Begin numbering them at 0.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20200319122737.3063291-9-thierry.reding@gmail.com
Tested-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

...

This commit is contained in:

Thierry Reding 2020-03-19 13:27:36 +01:00 • committed by Linus Walleij

parent f67499f8ea

commit 103afc8e9e

1 changed files with 4 additions and 7 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

11

drivers/pinctrl/tegra/pinctrl-tegra194.c

View file