From 1098a94f822d24764a4ec2bf1e4643e231622cdf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Wed, 26 Aug 2026 16:40:29 +0300 Subject: [PATCH] drm/i915/cdclk: Extract bdw_cdclk_pcode_{pre,post}_notify() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Extract the BDW pcode notify stuff to a few small helpers. The plan is to unify these between all the platforms and turn them into vfuncs. Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä Link: https://patch.msgid.link/20260826134033.13976-11-ville.syrjala@linux.intel.com --- drivers/gpu/drm/i915/display/intel_cdclk.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 07471a6cef8f..96094e1b2bb3 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -872,6 +872,19 @@ static u32 bdw_cdclk_freq_sel(int cdclk) } } +static int bdw_cdclk_pcode_pre_notify(struct intel_display *display) +{ + return intel_parent_pcode_write(display, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, + 0x0); +} + +static int bdw_cdclk_pcode_post_notify(struct intel_display *display, + const struct intel_cdclk_config *cdclk_config) +{ + return intel_parent_pcode_write(display, HSW_PCODE_DE_WRITE_FREQ_REQ, + cdclk_config->voltage_level); +} + static void bdw_set_cdclk(struct intel_display *display, const struct intel_cdclk_config *cdclk_config, enum pipe pipe) @@ -888,7 +901,7 @@ static void bdw_set_cdclk(struct intel_display *display, "trying to change cdclk frequency with cdclk not enabled\n")) return; - ret = intel_parent_pcode_write(display, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); + ret = bdw_cdclk_pcode_pre_notify(display); if (ret) { drm_err(display->drm, "Failed to inform PCODE about start of CDCLK change (%d)\n", ret); @@ -918,8 +931,7 @@ static void bdw_set_cdclk(struct intel_display *display, if (ret) drm_err(display->drm, "Switching back to LCPLL failed\n"); - ret = intel_parent_pcode_write(display, HSW_PCODE_DE_WRITE_FREQ_REQ, - cdclk_config->voltage_level); + ret = bdw_cdclk_pcode_post_notify(display, cdclk_config); if (ret) drm_err(display->drm, "Failed to inform PCODE about end of CDCLK change (%d)\n", ret);