mmc: sdhci-pxav3: Modify clock settings for the SDR50 and DDR50 modes

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According to erratum 'FE-2946959' both SDR50 and DDR50 modes require
specific clock adjustments in SDIO3 Configuration register.

This commit add the support of this register and for SDR50 or DDR50
mode use it as suggested by the erratum:
- Set the SDIO3 Clock Inv field in SDIO3 Configuration register to not
inverted.
- Set the Sample FeedBack Clock field to 0x1

[gregory.clement@free-electrons.com: port from 3.10]

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

...

This commit is contained in:

Marcin Wojtas 2015-01-29 12:36:27 +01:00 • committed by Ulf Hansson

parent d58a2ea5cb

commit 1140011ee9

1 changed files with 50 additions and 8 deletions

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drivers/mmc/host/sdhci-pxav3.c

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