x86/cpufeatures: Add detection of L1D cache flush support.

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336996-Speculative-Execution-Side-Channel-Mitigations.pdf defines a new MSR
(IA32_FLUSH_CMD) which is detected by CPUID.7.EDX[28]=1 bit being set.

This new MSR "gives software a way to invalidate structures with finer
granularity than other architectual methods like WBINVD."

A copy of this document is available at
  https://bugzilla.kernel.org/show_bug.cgi?id=199511

Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>

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Konrad Rzeszutek Wilk 2018-06-20 16:42:58 -04:00 • committed by Thomas Gleixner

parent 1a7ed1ba4b

commit 11e34e64e4

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arch/x86/include/asm/cpufeatures.h

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