Merge branches 'clk-vc5', 'clk-silabs', 'clk-aspeed', 'clk-qoriq' and 'clk-rohm' into clk-next

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- Support crystal load capacitance for Versaclock VC5
 - Add a "skip recall" DT binding for Silicon Labs' si570 to avoid glitches at boot

* clk-vc5:
  clk: vc5: Add support for optional load capacitance
  dt-bindings: clk: versaclock5: Add optional load capacitance property

* clk-silabs:
  clk: si570: Skip NVM to RAM recall operation if an optional property is set
  dt-bindings: clock: si570: Add 'silabs,skip-recall' property

* clk-aspeed:
  clk: aspeed: Fix APLL calculate formula from ast2600-A2

* clk-qoriq:
  clk: qoriq: use macros to generate pll_mask

* clk-rohm:
  clk: BD718x7: Do not depend on parent driver data

...

This commit is contained in:

Stephen Boyd 2021-02-16 14:09:12 -08:00

parent 242d8cf626 f3d661d6b4 d9d4944d36 6286ce1e3e fa4dd53eee ddddfafd94

commit 11f83102d8

7 changed files with 161 additions and 38 deletions

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6

Documentation/devicetree/bindings/clock/idt,versaclock5.yaml

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2

Documentation/devicetree/bindings/clock/silabs,si570.txt

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37

drivers/clk/clk-ast2600.c

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12

drivers/clk/clk-bd718x7.c

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62

drivers/clk/clk-qoriq.c

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16

drivers/clk/clk-si570.c

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64

drivers/clk/clk-versaclock5.c

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