x86/speculation: Add virtualized speculative store bypass disable support

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Some AMD processors only support a non-architectural means of enabling
speculative store bypass disable (SSBD).  To allow a simplified view of
this to a guest, an architectural definition has been created through a new
CPUID bit, 0x80000008_EBX[25], and a new MSR, 0xc001011f.  With this, a
hypervisor can virtualize the existence of this definition and provide an
architectural method for using SSBD to a guest.

Add the new CPUID feature, the new MSR and update the existing SSBD
support to use this MSR when present.

Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Borislav Petkov <bp@suse.de>

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Tom Lendacky 2018-05-17 17:09:18 +02:00 • committed by Thomas Gleixner

parent ccbcd26744

commit 11fb068349

4 changed files with 18 additions and 2 deletions

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1

arch/x86/include/asm/cpufeatures.h

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2

arch/x86/include/asm/msr-index.h

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4

arch/x86/kernel/cpu/bugs.c

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arch/x86/kernel/process.c

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