dt-bindings: interrupt-controller: sifive,plic: Document Renesas RZ/Five SoC

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Renesas RZ/Five (R9A07G043) SoC is equipped with NCEPLIC100 RISC-V
platform level interrupt controller from Andes Technology. NCEPLIC100
ignores subsequent EDGE interrupts until the previous EDGE interrupt is
completed, due to this issue we have to follow different interrupt flow
for EDGE and LEVEL interrupts.

This patch documents Renesas RZ/Five (R9A07G043) SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220630100241.35233-2-samuel@sholland.org

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Lad Prabhakar 2022-06-30 05:02:38 -05:00 • committed by Marc Zyngier

parent a111daf0c5

commit 1267d98311

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Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml

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