riscv: misaligned: Add handling for ZCB instructions

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[ Upstream commit eb16b3727c ]

Add support for the Zcb extension's compressed half-word instructions
(C.LHU, C.LH, and C.SH) in the RISC-V misaligned access trap handler.

Signed-off-by: Zong Li <zong.li@sifive.com>
Signed-off-by: Nylon Chen <nylon.chen@sifive.com>
Fixes: 956d705dd2 ("riscv: Unaligned load/store handling for M_MODE")
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Link: https://lore.kernel.org/r/20250411073850.3699180-2-nylon.chen@sifive.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

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Nylon Chen 2025-04-11 15:38:49 +08:00 • committed by Greg Kroah-Hartman

parent eaa30e1d0e

commit 126be03494

1 changed files with 17 additions and 0 deletions

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arch/riscv/kernel/traps_misaligned.c

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