MIPS: genex: Add Loongson3 LL/SC workaround to ejtag_debug_handler

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In ejtag_debug_handler we use LL & SC instructions to acquire & release
an open-coded spinlock. For Loongson3 systems affected by LL/SC errata
this requires that we insert a sync instruction prior to the LL in order
to ensure correct behavior of the LL/SC loop.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
Cc: Huacai Chen <chenhc@lemote.com>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: linux-kernel@vger.kernel.org

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Paul Burton 2019-10-01 21:53:42 +00:00

parent ae4cd0b1a4

commit 12dbb04f2a

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arch/mips/kernel/genex.S

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