dt-bindings: pci: tegra: Update for per-lane PHYs

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The XUSB pad controller allows PCIe lanes to be controlled individually,
providing fine-grained control over their power state. Previous attempts
at describing the XUSB pad controller in DT had erroneously assumed that
all PCIe lanes were driven by the same PHY, and hence the PCI host
controller would reference only a single PHY.

Moving to a representation of per-lane PHYs requires that the operating
system driver for the PCI host controller have access to the set of PHY
devices that make up the connection of each root port in order to power
up and down all of the lanes as necessary.

Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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Thierry Reding 2016-03-04 16:50:50 +01:00

parent 4000b00f3c

commit 13541cc3d4

1 changed files with 219 additions and 5 deletions

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Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt

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