arm64: dts: ls1028a: Update the clock providers for the Mali DP500

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In order to maximise performance of the LCD Controller's 64-bit AXI
bus, for any give speed bin of the device, the AXI master interface
clock(ACLK) clock can be up to CPU_frequency/2, which is already
capable of optimal performance. In general, ACLK is always expected
to be equal to CPU_frequency/2. APB slave interface clock(PCLK) and
Main processing clock(PCLK) both are tied to the same clock as ACLK.

This change followed the LS1028A Architecture Specification Manual.

Signed-off-by: Wen He <wen.he_1@nxp.com>
Acked-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

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Wen He 2019-09-20 16:34:18 +08:00 • committed by Shawn Guo

parent 62b4359c30

commit 1378259773

1 changed files with 2 additions and 15 deletions

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arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi

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