diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 91a387621bcb..05347f1f3d4a 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -754,6 +754,11 @@ properties: - const: khadas,edge2 - const: rockchip,rk3588s + - description: Khadas Edge-2L series boards + items: + - const: khadas,edge-2l + - const: rockchip,rk3576 + - description: Kobol Helios64 items: - const: kobol,helios64 diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 11a1bad35209..cb55c6b70d0e 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -170,6 +170,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-armsom-sige5-v1.2-wifibt.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-evb1-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-evb1-v10-pcie1.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-evb2-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-khadas-edge-2l.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-luckfox-omni3576.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-nanopi-m5.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-nanopi-r76s.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts index 30bdb38f0727..e810ed146451 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts @@ -58,24 +58,6 @@ gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; linux,rc-map-name = "rc-beelink-gs1"; }; - - spdif_dit: spdif-dit { - compatible = "linux,spdif-dit"; - #sound-dai-cells = <0>; - }; - - spdif_sound: spdif-sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "SPDIF"; - - simple-audio-card,cpu { - sound-dai = <&spdif>; - }; - - simple-audio-card,codec { - sound-dai = <&spdif_dit>; - }; - }; }; &analog_sound { @@ -343,11 +325,6 @@ status = "okay"; }; -&spdif { - pinctrl-0 = <&spdifm0_tx>; - status = "okay"; -}; - &tsadc { rockchip,hw-tshut-mode = <0>; rockchip,hw-tshut-polarity = <0>; diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi index d402f2828814..806b8109f67d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi @@ -1190,6 +1190,53 @@ status = "disabled"; }; + otp: efuse@ffce0000 { + compatible = "rockchip,rk3528-otp"; + reg = <0x0 0xffce0000 0x0 0x4000>; + clocks = <&cru CLK_USER_OTPC_NS>, <&cru PCLK_OTPC_NS>, + <&cru CLK_SBPI_OTPC_NS>; + clock-names = "otp", "apb_pclk", "sbpi"; + resets = <&cru SRST_USER_OTPC_NS>, <&cru SRST_P_OTPC_NS>, + <&cru SRST_SBPI_OTPC_NS>; + reset-names = "otp", "apb", "sbpi"; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + cpu_code: cpu-code@2 { + reg = <0x02 0x2>; + }; + + otp_cpu_version: cpu-version@8 { + reg = <0x08 0x1>; + bits = <3 3>; + }; + + otp_id: id@a { + reg = <0x0a 0x10>; + }; + + cpu_leakage: cpu-leakage@1a { + reg = <0x1a 0x1>; + }; + + logic_leakage: logic-leakage@1b { + reg = <0x1b 0x1>; + }; + + gpu_leakage: gpu-leakage@1c { + reg = <0x1c 0x1>; + }; + + tsadc_trim: tsadc-trim@44 { + reg = <0x44 0x2>; + bits = <0 10>; + }; + }; + }; + dmac: dma-controller@ffd60000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0xffd60000 0x0 0x4000>; diff --git a/arch/arm64/boot/dts/rockchip/rk3562-evb2-v10.dts b/arch/arm64/boot/dts/rockchip/rk3562-evb2-v10.dts index 6a84db154a7d..387062eea520 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562-evb2-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3562-evb2-v10.dts @@ -13,7 +13,7 @@ #include "rk3562.dtsi" / { - model = "Rockchip RK3562 EVB V20 Board"; + model = "Rockchip RK3562 EVB2 V10 Board"; compatible = "rockchip,rk3562-evb2-v10", "rockchip,rk3562"; chosen: chosen { diff --git a/arch/arm64/boot/dts/rockchip/rk3562.dtsi b/arch/arm64/boot/dts/rockchip/rk3562.dtsi index f84676b47b27..e4816aa3dae0 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562.dtsi @@ -1093,6 +1093,52 @@ status = "disabled"; }; + otp: efuse@ff930000 { + compatible = "rockchip,rk3562-otp"; + reg = <0x0 0xff930000 0x0 0x4000>; + clocks = <&cru CLK_USER_OTPC_NS>, <&cru PCLK_OTPC_NS>, + <&cru PCLK_OTPPHY>, <&cru CLK_SBPI_OTPC_NS>; + clock-names = "otp", "apb_pclk", "phy", "sbpi"; + resets = <&cru SRST_USER_OTPC_NS>, <&cru SRST_P_OTPC_NS>, + <&cru SRST_P_OTPPHY>, <&cru SRST_SBPI_OTPC_NS>; + reset-names = "otp", "apb", "phy", "sbpi"; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + cpu_code: cpu-code@2 { + reg = <0x02 0x2>; + }; + + otp_cpu_version: cpu-version@8 { + reg = <0x08 0x1>; + bits = <3 3>; + }; + + otp_id: id@a { + reg = <0x0a 0x10>; + }; + + cpu_leakage: cpu-leakage@1a { + reg = <0x1a 0x1>; + }; + + log_leakage: log-leakage@1b { + reg = <0x1b 0x1>; + }; + + npu_leakage: npu-leakage@1c { + reg = <0x1c 0x1>; + }; + + gpu_leakage: gpu-leakage@1d { + reg = <0x1d 0x1>; + }; + }; + }; + dmac: dma-controller@ff990000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0xff990000 0x0 0x4000>; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-lckfb-tspi.dts b/arch/arm64/boot/dts/rockchip/rk3566-lckfb-tspi.dts index ed65d3120444..18a560a6e2a4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-lckfb-tspi.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-lckfb-tspi.dts @@ -635,10 +635,10 @@ status = "okay"; bluetooth: bluetooth { - compatible = "brcm,bcm43438-bt"; + compatible = "brcm,bcm43430a1-bt"; clocks = <&rk809 1>; clock-names = "lpo"; - max-speed = <3000000>; + max-speed = <1500000>; pinctrl-names = "default"; pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi index 658097ed6971..3bc653f027f1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi @@ -155,9 +155,11 @@ bus-range = <0x10 0x1f>; clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>, <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>, - <&cru CLK_PCIE30X1_AUX_NDFT>; + <&cru CLK_PCIE30X1_AUX_NDFT>, + <&cru CLK_PCIE30X1_PIPE_DFT>; clock-names = "aclk_mst", "aclk_slv", - "aclk_dbi", "pclk", "aux"; + "aclk_dbi", "pclk", "aux", + "pipe"; device_type = "pci"; interrupts = , , @@ -208,9 +210,11 @@ bus-range = <0x20 0x2f>; clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>, <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>, - <&cru CLK_PCIE30X2_AUX_NDFT>; + <&cru CLK_PCIE30X2_AUX_NDFT>, + <&cru CLK_PCIE30X2_PIPE_DFT>; clock-names = "aclk_mst", "aclk_slv", - "aclk_dbi", "pclk", "aux"; + "aclk_dbi", "pclk", "aux", + "pipe"; device_type = "pci"; interrupts = , , diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi index 68b48606f601..64bdd8b7754b 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi @@ -1020,9 +1020,11 @@ bus-range = <0x0 0xf>; clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>, - <&cru CLK_PCIE20_AUX_NDFT>; + <&cru CLK_PCIE20_AUX_NDFT>, + <&cru CLK_PCIE20_PIPE_DFT>; clock-names = "aclk_mst", "aclk_slv", - "aclk_dbi", "pclk", "aux"; + "aclk_dbi", "pclk", "aux", + "pipe"; device_type = "pci"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; @@ -1123,6 +1125,52 @@ status = "disabled"; }; + otp: efuse@fe38c000 { + compatible = "rockchip,rk3568-otp"; + reg = <0x0 0xfe38c000 0x0 0x4000>; + clocks = <&cru CLK_OTPC_NS_USR>, <&cru PCLK_OTPC_NS>, + <&cru PCLK_OTPPHY>, <&cru CLK_OTPC_NS_SBPI>; + clock-names = "otp", "apb_pclk", "phy", "sbpi"; + resets = <&cru SRST_OTPC_NS_USR>, <&cru SRST_P_OTPC_NS>, + <&cru SRST_OTPPHY>, <&cru SRST_OTPC_NS_SBPI>; + reset-names = "otp", "apb", "phy", "sbpi"; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + cpu_code: cpu-code@2 { + reg = <0x02 0x2>; + }; + + otp_cpu_version: cpu-version@8 { + reg = <0x08 0x1>; + bits = <3 3>; + }; + + otp_id: id@a { + reg = <0x0a 0x10>; + }; + + cpu_leakage: cpu-leakage@1a { + reg = <0x1a 0x1>; + }; + + log_leakage: log-leakage@1b { + reg = <0x1b 0x1>; + }; + + npu_leakage: npu-leakage@1c { + reg = <0x1c 0x1>; + }; + + gpu_leakage: gpu-leakage@1d { + reg = <0x1d 0x1>; + }; + }; + }; + i2s0_8ch: i2s@fe400000 { compatible = "rockchip,rk3568-i2s-tdm"; reg = <0x0 0xfe400000 0x0 0x1000>; diff --git a/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts b/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts index d372ba252af8..1c100ffd1518 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts @@ -21,6 +21,8 @@ aliases { ethernet0 = &gmac0; ethernet1 = &gmac1; + mmc0 = &sdhci; + mmc1 = &sdmmc; }; chosen { diff --git a/arch/arm64/boot/dts/rockchip/rk3576-khadas-edge-2l.dts b/arch/arm64/boot/dts/rockchip/rk3576-khadas-edge-2l.dts new file mode 100644 index 000000000000..68630379af63 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3576-khadas-edge-2l.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include "rk3576.dtsi" + +/ { + model = "Khadas Edge-2L"; + compatible = "khadas,edge-2l", "rockchip,rk3576"; + + aliases { + mmc0 = &sdhci; + }; + + chosen { + stdout-path = "serial0:1500000n8"; + }; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi index 53ff6bd027af..28175d8200d5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -1379,6 +1379,19 @@ status = "disabled"; }; + spdif_tx2: spdif-tx@27d20000 { + compatible = "rockchip,rk3576-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0x27d20000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_SPDIF_TX2>, <&cru HCLK_SPDIF_TX2>; + clock-names = "mclk", "hclk"; + dmas = <&dmac2 28>; + dma-names = "tx"; + power-domains = <&power RK3576_PD_VO0>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + sai5: sai@27d40000 { compatible = "rockchip,rk3576-sai"; reg = <0x0 0x27d40000 0x0 0x1000>; @@ -1511,6 +1524,45 @@ }; }; + spdif_tx3: spdif-tx@27ea0000 { + compatible = "rockchip,rk3576-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0x27ea0000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_SPDIF_TX3>, <&cru HCLK_SPDIF_TX3>; + clock-names = "mclk", "hclk"; + dmas = <&dmac2 29>; + dma-names = "tx"; + power-domains = <&power RK3576_PD_VO1>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spdif_tx4: spdif-tx@27eb0000 { + compatible = "rockchip,rk3576-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0x27eb0000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_SPDIF_TX4>, <&cru HCLK_SPDIF_TX4>; + clock-names = "mclk", "hclk"; + dmas = <&dmac1 6>; + dma-names = "tx"; + power-domains = <&power RK3576_PD_VO1>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spdif_tx5: spdif-tx@27ec0000 { + compatible = "rockchip,rk3576-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0x27ec0000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_SPDIF_TX5>, <&cru HCLK_SPDIF_TX5>; + clock-names = "mclk", "hclk"; + dmas = <&dmac0 25>; + dma-names = "tx"; + power-domains = <&power RK3576_PD_VO1>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + sai7: sai@27ed0000 { compatible = "rockchip,rk3576-sai"; reg = <0x0 0x27ed0000 0x0 0x1000>; @@ -1896,8 +1948,9 @@ pinctrl-0 = <&ufs_refclk &ufs_rstgpio>; pinctrl-names = "default"; resets = <&cru SRST_A_UFS_BIU>, <&cru SRST_A_UFS_SYS>, - <&cru SRST_A_UFS>, <&cru SRST_P_UFS_GRF>; - reset-names = "biu", "sys", "ufs", "grf"; + <&cru SRST_A_UFS>, <&cru SRST_P_UFS_GRF>, + <&cru SRST_MPHY_INIT>; + reset-names = "biu", "sys", "ufs", "grf", "mphy"; reset-gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_LOW>; status = "disabled"; }; @@ -2166,6 +2219,36 @@ status = "disabled"; }; + spdif_tx0: spdif-tx@2a670000 { + compatible = "rockchip,rk3576-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0x2a670000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_SPDIF_TX0>, <&cru HCLK_SPDIF_TX0>; + clock-names = "mclk", "hclk"; + dmas = <&dmac0 5>; + dma-names = "tx"; + power-domains = <&power RK3576_PD_AUDIO>; + pinctrl-names = "default"; + pinctrl-0 = <&spdifm0_tx0>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spdif_tx1: spdif-tx@2a680000 { + compatible = "rockchip,rk3576-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0x2a680000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_SPDIF_TX1>, <&cru HCLK_SPDIF_TX1>; + clock-names = "mclk", "hclk"; + dmas = <&dmac1 5>; + dma-names = "tx"; + power-domains = <&power RK3576_PD_AUDIO>; + pinctrl-names = "default"; + pinctrl-0 = <&spdifm0_tx1>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@2a701000 { compatible = "arm,gic-400"; reg = <0x0 0x2a701000 0 0x10000>, diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts index de154adb1497..f7dd01d6fa0a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts @@ -367,6 +367,18 @@ status = "okay"; }; +&hdmi_receiver_cma { + status = "okay"; +}; + +&hdmi_receiver { + pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_det>; + pinctrl-names = "default"; + hpd-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + &hdptxphy1 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi index b3e76ad2d869..bf4a1d2e55ca 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi @@ -468,7 +468,8 @@ &pcie2x1l0 { pinctrl-names = "default"; - pinctrl-0 = <&pcie2_0_rst>; + pinctrl-0 = <&pcie2_0_rst>, <&pcie30x1m1_0_clkreqn>; + supports-clkreq; reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; status = "okay"; @@ -476,7 +477,8 @@ &pcie2x1l2 { pinctrl-names = "default"; - pinctrl-0 = <&pcie2_2_rst>; + pinctrl-0 = <&pcie2_2_rst>, <&pcie20x1m0_clkreqn>; + supports-clkreq; reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie2x1l2>; status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts b/arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts index e8ad525ba3f9..89618394c0bf 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts @@ -60,8 +60,8 @@ reg = <0>; abs-flat = <40>; abs-fuzz = <30>; - abs-range = <0 4095>; - linux,code = ; + abs-range = <4095 0>; + linux,code = ; }; axis@1 { @@ -69,7 +69,7 @@ abs-flat = <40>; abs-fuzz = <30>; abs-range = <0 4095>; - linux,code = ; + linux,code = ; }; axis@2 { @@ -77,7 +77,7 @@ abs-flat = <40>; abs-fuzz = <30>; abs-range = <0 4095>; - linux,code = ; + linux,code = ; }; axis@3 { @@ -85,7 +85,7 @@ abs-flat = <40>; abs-fuzz = <30>; abs-range = <0 4095>; - linux,code = ; + linux,code = ; }; }; @@ -318,7 +318,7 @@ compatible = "pwm-fan"; #cooling-cells = <2>; cooling-levels = <0 120 150 180 210 240 255>; - fan-supply = <&vcc5v0_sys>; + fan-supply = <&vcc5v0_spk>; interrupt-parent = <&gpio4>; interrupts = ; pulses-per-revolution = <4>;