clk: sunxi-ng: Support multiple variable pre-dividers

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On the A83T, the AHB1 clock has a shared pre-divider on the two
PLL-PERIPH clock parents. To support such instances of shared
pre-dividers, this patch extends the mux clock type to support
multiple variable pre-dividers.

As the pre-dividers are only used to calculate the rate, but
do not participate in the factorization process, this is fairly
straightforward.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

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This commit is contained in:

Chen-Yu Tsai 2017-05-19 15:06:08 +08:00 • committed by Maxime Ripard

parent 11ad470c54

commit 13e0dde8b2

9 changed files with 54 additions and 47 deletions

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10

drivers/clk/sunxi-ng/ccu-sun50i-a64.c

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10

drivers/clk/sunxi-ng/ccu-sun6i-a31.c

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drivers/clk/sunxi-ng/ccu-sun8i-a23.c

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drivers/clk/sunxi-ng/ccu-sun8i-a33.c

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drivers/clk/sunxi-ng/ccu-sun8i-h3.c

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drivers/clk/sunxi-ng/ccu-sun8i-r.c

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drivers/clk/sunxi-ng/ccu-sun8i-v3s.c

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18

drivers/clk/sunxi-ng/ccu_mux.c

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13

drivers/clk/sunxi-ng/ccu_mux.h

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