drm/xe: Add support for CCS engine fusing

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For Xe_HP platforms that can have multiple CCS engines, the
presence/absence of each CCS is inferred by the presence/absence of any
DSS in the corresponding quadrant of the GT's DSS mask.

This handling is only needed on platforms that can have more than one
CCS.  The CCS is never fused off on platforms like MTL that can only
have one.

v2:
 - Add extra warnings to try to catch mistakes where the register counts
   in get_num_dss_regs() are updated without corresponding updates to
   the register parameters passed to load_dss_mask().  (Lucas)
 - Add kerneldoc for xe_gt_topology_has_dss_in_quadrant() and clarify
   why we care about quadrants of the DSS space.  (Lucas)
 - Ensure CCS engine counting treats engine mask as 64-bit.  (Lucas)

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://lore.kernel.org/r/20230309005530.3140173-2-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

...

This commit is contained in:

Matt Roper 2023-03-08 16:55:30 -08:00 • committed by Rodrigo Vivi

parent 7c7225ddaa

commit 13fb0c9872

3 changed files with 85 additions and 12 deletions

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65

drivers/gpu/drm/xe/xe_gt_topology.c

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3

drivers/gpu/drm/xe/xe_gt_topology.h

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29

drivers/gpu/drm/xe/xe_hw_engine.c

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