drm/i915/adl_p: Don't config MBUS and DBUF during display initialization

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Alderlake-P don't have programing sequences for MBUS or DBUF during
display initializaiton, instead it requires programing to those
registers during modeset because it to depend on the pipes left
enabled.

Bspec: 49213
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210519000625.3184321-7-lucas.demarchi@intel.com

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José Roberto de Souza 2021-05-18 17:06:14 -07:00 • committed by Lucas De Marchi

parent 55ce306c2a

commit 14076e4645

1 changed files with 6 additions and 0 deletions

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drivers/gpu/drm/i915/display/intel_display_power.c

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