RISC-V: errata: Add SiFive MAL-9092 workaround

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SiFive cores with MAL-9092 require fence.rw instructions around
HLV/HLVX/HSV hypervisor instructions to ensure proper memory ordering
when accessing guest memory.

Note that HSTATUS.HU is cleared during KVM initialization, restricting
hypervisor instructions to HS-mode only. If future changes enable
HSTATUS.HU for U-mode access, additional errata considerations will be
needed.

Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Link: https://patch.msgid.link/20260817-sifive-errata-v1-1-6a80f1a2743d@sifive.com
Signed-off-by: Paul Walmsley <pjw@kernel.org>

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Yong-Xuan Wang 2026-10-05 19:02:38 -06:00 • committed by Paul Walmsley

parent 55b1276ef9

commit 148ab873d8

4 changed files with 49 additions and 4 deletions

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14

arch/riscv/Kconfig.errata

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20

arch/riscv/errata/sifive/errata.c

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3

arch/riscv/include/asm/errata_list_vendors.h

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16

arch/riscv/include/asm/insn-def.h

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