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Update for meson clocks targeted at v4.20
- clk-pll driver improvements and updates - add axg audio controller system clocks - drop mpll3 from the possible pcie clock parent of the axg - register meson8b clock controller early -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE9OFZrhjz9W1fG7cb5vwPHDfy2oUFAlus504ACgkQ5vwPHDfy 2oUGOQ//bQJ7YQdm3mcG0nJn1GY2WHGa17THQSklhSca83inYdE+ag1ERLloV+Fh fMIDH9J1E5BbzQXJk/C9JZq5mxHuITbcIzCv5dB9jy8iOGu2doHYbQbCff9F6pdR EDvEUpBSGxClavRWAc5LLuK+/z6y+l9+zBPsVrGeh23dK2vh19eBFtuUlpteSeTU uD4sgv7tEXq6R2MPV42B74HFsKE9aUW69G5Qz/+DkP6FoAugc1HMOs7m9P8crmqk OcL03SGqnhmQBWWV4xCaqDVYUDIrPQ4Sd2ZdO0kdK/tE2aC0ZhC7+FACFGZgZmDq YglT/Z8NAStTvWZnGKb6SCzlygdUEzJqWHhQK0HC9Kb6foVhD4MLUKw0cmWgm1aT Tdxklw/Ha8q0t/osbQYEcD/19U/bKWdwn5Au0w6gmXvcMeLbuLKEM83Q0wyS9PUu zyTx+9ArIzhBRMeUbaZNKwLKRhDX9d/+urB7fuXQJpNZFDRCVxdMmBRnCJ2L2bUg xmdkpP7gtUL7pt/+Jdz6h8kNNI795jrd4INcIGkutRNbfMy2jhUA/jPBoaoDcBov X+nbWCyxP6R2vZlsxpNPkBQN2QQIEJV1lUI0deBN3Opb2ML9/MTf9IgcfyCvwFfX InIxcT7931cvxleheGfIez6uvAx5jH1x4xGGakr5EKCSIczwwUo= =GF25 -----END PGP SIGNATURE----- Merge tag 'meson-clk-4.20-1' of https://github.com/BayLibre/clk-meson into clk-meson Pull meson clk driver updates from Jerome Brunet: - clk-pll driver improvements and updates - add axg audio controller system clocks - drop mpll3 from the possible pcie clock parent of the axg - register meson8b clock controller early * tag 'meson-clk-4.20-1' of https://github.com/BayLibre/clk-meson: clk: meson: meson8b: use the regmap in the internal reset controller clk: meson: meson8b: register the clock controller early clk: meson-axg: pcie: drop the mpll3 clock parent clk: meson: axg: round audio system master clocks down clk: meson: clk-pll: drop hard-coded rates from pll tables clk: meson: clk-pll: remove od parameters clk: meson: clk-pll: drop CLK_GET_RATE_NOCACHE where unnecessary clk: meson: clk-pll: add enable bit
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