clk: renesas: rzg2l: Add FOUTPOSTDIV clk support

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PLL5 generates FOUTPOSTDIV clk and is sourced by LCDC/DSI modules.
The FOUTPOSTDIV is connected to PLL5_4 MUX. Video clock is sourced
from DSI divider which is connected to PLL5_4 MUX.

This patch adds support for generating FOUTPOSTDIV clk.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220430114156.6260-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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Biju Das 2022-04-30 12:41:48 +01:00 • committed by Geert Uytterhoeven

parent 0ab55cf183

commit 1561380ee7

2 changed files with 235 additions and 0 deletions

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212

drivers/clk/renesas/rzg2l-cpg.c

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23

drivers/clk/renesas/rzg2l-cpg.h

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